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Verilog2001及SystemVerilog入門指引
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第1章 overview
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發展歷史
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EDA 工具的支持進度
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SystemVerilog 的特性
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SystemC
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第2章 Verilog 2001
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回顧Verilog 2001
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Register changed to variable
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$ferror
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$fflush
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$fgetc
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$fgets
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$fread
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$fscanf
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$fseek
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第3章 Data Type
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資料型態
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auto variable vs static variable
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Constant
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Scope and lifetime
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Nets and regs
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State
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2-State data type
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logic data type
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Void data type
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String data type
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String operators
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String method
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Event data type
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User defined data type
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Enumerate data type
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Enumerated type ranges
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Enumerated types in numerical expressions
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Enumeration method
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Pack vs Unpacked
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Structures
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Packed Unpacked structures
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Packed Union
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Casting
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Dynamic casting
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Array
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Indexing and slicing of Array
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Array function
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Dynamic-array
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Associative-array
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Queue
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Queue function
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第4章 Operator
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Operator and expression
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Assignment operator
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Wildcard equality and inequality operators
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Uniary operator
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binary operator
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Static prefixes
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Concatenation
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Struct
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Set membership
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第5章 Procedural ＆ Control
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Procedural ＆ Control
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Selection statements
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Loop statements
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disable block
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name blocks
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return
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foreach
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final
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event control
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fork join fork join_none fork_join_any
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wait fork disable fork
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Synthesis convenient
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第6章 Tasks and functions
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Tasks and functions
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忽略begin end
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SystemVerilog function
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Pass by value
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Pass by reference
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Pass by name
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Self-defined data type task or functions
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第7章 Interface
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Interface
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Name bundle vs generic bundle
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Interface reference
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Ports in reference
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Modports
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Parameters
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第8章 Class
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OOP(Object Oriented Programming)
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class
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constructors
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object method
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assignment
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static class properties
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This
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inheritance
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overridden members
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super
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Data hiding local
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Data hiding protected
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virtual class
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第9章 Random Constraints
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Random Constraints
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randomize() with
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distribution
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function in constraints
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rand in class
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Inheritance
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Implication(-＞)
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Random weighted case(randcase)
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$urandom and $urandom_range
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rand_mode
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constraint_mode
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第10章 Coverage
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驗證Coverage
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覆蓋率Coverage
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Covergroup
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Coverpoints
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Coverage bins
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Cross coverage
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Covergroup guard
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Specify coverage options
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covergroup parameters
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ignore bins
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illegal bins
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第11 章 Assertions
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Assertion verification
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Sequence declarations
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Uprange sign
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Implication Operators
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Consecutive repetition
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Non-consecutive repetition
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Goto repetition
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And operation
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OR operation
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Sample value function
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Condition over sequence
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Intersect operator
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first_match operator
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序列裏含匯流排資料
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Assertion
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Property
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附錄
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A.1 SYNOPSYS VCS
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2.1 Cadence NC
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2.2 Running Coverage with Cadence Incisive
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2.3 Running Coverage with Cadence Incisive
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B.1 Source text
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1.1 Library source text
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1.2 Configuration source text
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1.3 Module and primitive source text
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1.4 Module parameters and ports
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1.5 Module items
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1.6 Interface items
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1.7 Program items
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1.8 Class items
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1.9 Constraints
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B.2 Declarations
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2.1 Declaration types
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2.2 Declaration data types
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2.3 Declaration lists
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2.4 Declaration assignments
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2.5 Declaration ranges
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2.6 Function declarations
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2.7 Task declarations
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2.8 Block item declarations
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2.9 Interface declarations
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2.10 Assertion declarations
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B.3 Primitive instances
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3.1 Primitive instantiation and instances
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3.2 Primitive strengths
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3.3 Primitive terminals
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3.4 Primitive gate and switch types
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B.4 Module，interface and generated instantiation
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4.1 Instantiation
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4.2 Generated instantiation
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B.5 UDP declaration and instantiation
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5.1 UDP declaration
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5.2 UDP ports
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5.3 UDP body
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5.4 UDP instantiation
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B.6 Behavioral statements
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6.1 Continuous assignment and net alias statements
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6.2 Procedural blocks and assignments
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6.3 Parallel and sequential blocks
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6.4 Statements
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6.5 Timing control statements
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6.7 Case statements
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6.8 Looping statements
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6.9 Task enable statements
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6.10 Assertion statements
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6.11 Clocking domain
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B.7 Specify section
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7.1 Specify block declaration
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7.2 Specify path declarations
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7.3 Specify block terminals
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7.4 Specify path delays
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7.5 System timing checks
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B.8 Expressions
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8.1 Concatenations
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8.2 Function calls
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8.3 Expressions
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8.4 Primaries
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8.5 Expression left-side values
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8.6 Operators
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8.7 Numbers
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8.8 Strings
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B.9 General
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9.1 Attributes
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9.2 Comments
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9.3 Identifiers
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9.4 Identifier branches
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9.5 White space
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- 出版地 ： 臺灣
- 語言 ： 繁體中文
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